This invention lies in the field of digital recording systems. More particularly, it concerns apparatus for maintaining a derived clock whose frequency is N times that of the data edges of an incoming stream of data bits and is in synchronism with the stream of incoming data bits.
While there are a number of published designs of voltage-controlled oscillator (VCO) clocks, or phaselocked oscillator (PLO) clocks, for providing such identity of phase between a derived clock and the data clock, they all have difficulties in the sense that they require the use of adjustable resistance devices, such as potentiometers and other devices, which have a high failure rate. The present invention is self-adjusting. Also, it integrates the phase error as compared to a sample and hold device, thus making data recovery faster and with fewer errors.